TSMC and Cadence Collaborate to Deliver AI-Driven Advanced-Node Design Flows, Silicon-Proven IP and 3D-IC Solutions

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Insights

This collaboration between TSMC and Cadence represents a significant advancement in semiconductor design and manufacturing capabilities, particularly for AI applications. Key points include:

AI-driven design flows for TSMC's advanced N2P and N3 nodes, which will enable more efficient chip designs for AI workloads
Collaboration on A16 design solutions to optimize power, performance and area (PPA)
Advancements in 3D-IC technology, including the Integrity 3D-IC Platform and 3Dblox features, which allow for more complex chip designs
Development of critical IP like the first silicon-proven GDDR7 IP at 32Gbps on TSMC N3, essential for high-performance AI systems
Support for silicon photonics and automotive applications, expanding the reach of these advanced technologies

This partnership is likely to accelerate the development of more powerful and efficient AI chips, potentially impacting the entire semiconductor industry and AI hardware landscape.

The collaboration between TSMC and Cadence is strategically significant for both companies and the broader semiconductor industry. For Cadence (CDNS), this partnership:

Strengthens its position in the rapidly growing AI chip design market
Enhances its product offerings, potentially driving increased software sales and market share
Aligns the company with TSMC, the world's largest contract chipmaker, providing a competitive edge

Financially, this could translate to:

Increased revenue from software licenses and IP sales
Potential for higher margins as AI-driven solutions often command premium pricing
Long-term growth prospects as demand for AI chips continues to surge

Investors should watch for increased adoption of Cadence's AI-driven design tools and any impact on the company's financial performance in upcoming quarters.

This collaboration signifies a major shift in the semiconductor industry towards AI-optimized chip design and manufacturing. Market implications include:

Accelerated development of AI chips, potentially leading to faster market penetration of AI technologies across various sectors
Increased competition in the EDA (Electronic Design Automation) space, as other players may seek similar partnerships
Potential for new market entrants in AI hardware, enabled by more accessible advanced chip design capabilities
Growth in the 3D-IC and advanced packaging markets, as these technologies become more mainstream

The partnership could also influence the broader tech ecosystem, affecting companies in cloud computing, data centers and AI software development. Long-term, this could lead to more powerful AI systems, potentially disrupting various industries and creating new market opportunities.

09/25/2024 - 03:05 PM

Highlights:

AI-driven digital and custom design flows available for the latest TSMC N2P and N3 technologies
Cadence is collaborating with TSMC on A16 design solutions to optimize PPA
Cadence Integrity 3D-IC Platform unifying packaging, analog and digital design supports latest 3Dblox features
Collaboration includes Celsius Studio mechanical analysis enablement and thermal/voltage impacts on power/IR/STA and what-if in-design analysis
Design IP powers the AI factory, including the industry鈥檚 first silicon-proven GDDR7 IP running at 32Gbps on the TSMC N3 technology
Cadence solutions support secure chip design in the cloud, with design solutions to support TSMC silicon photonics technologies

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it is collaborating with TSMC to enhance productivity and optimize product performance for AI-driven advanced-node designs and 3D-ICs. The rapid adoption of AI applications has created unprecedented demand for advanced silicon solutions capable of handling colossal datasets and computations. To meet these escalating requirements, the industry is pushing the boundaries of advanced-node silicon and 3D-IC technologies. TSMC and Cadence are at the forefront of this revolution, together empowering customers to accelerate time to market while increasing performance.

Cadence is collaborating with TSMC to enhance productivity and optimize product performance for AI-driven advanced-node designs and 3D-ICs. The rapid adoption of AI applications has created unprecedented demand for advanced silicon solutions capable of handling colossal datasets and computations. TSMC and Cadence are together empowering customers to accelerate time to market while increasing performance. (Graphic: Business Wire)

TSMC has certified 颁补诲别苍肠别鈥檚 industry-leading and design flows for implementation and signoff on TSMC鈥檚 latest N3 and N2P process technologies. As long-standing design technology co-optimization (DTCO) partners, TSMC and Cadence continue that tradition by collaborating to optimize power, performance and area (PPA) on A16, adding EDA features to enable advanced features such as backside routing.

Cadence and TSMC are also collaborating on to drive next-generation digital and analog design automation fueled by AI, delivering industry-leading productivity and quality of results. Cadence.AI is a chips-to-systems AI platform spanning all aspects of design and verification. The collaboration between TSMC and Cadence is focused on three main domains:

The Cadence^庐 Cerebrus^鈩� Intelligent Chip Explorer applies AI to digital design for converging on the optimal PPA.
The uses generative AI for design debug and analytics, helping with PPA analysis.
颁补诲别苍肠别鈥檚 Virtuoso^庐 Studio enables migrating legacy custom and analog designs to modern nodes and performs circuit optimization and high-sigma Monte Carlo analysis.

The Cadence Integrity^鈩� 3D-IC Platform is a leading system-level exploration solution and a single-vendor platform that unifies packaging, analog and digital implementation鈥攎aking efficient 3D-IC design possible. This opens new opportunities for innovation by supporting all the latest 3Dblox features and constructs. To enable the ultra-high-density interconnect in TSMC 3DFabric^鈩� technologies, TSMC and Cadence are collaborating on a next-generation high-capacity substrate router for die-to-die and die-to-substrate connections.

Multiphysics analyses and optimization is a critical dimension of success for 3D-IC technologies. TSMC and Cadence are collaborating to enable warpage/stress analysis for TSMC 3DFabric in addition to electrical/thermal analysis, and 颁补诲别苍肠别鈥檚 Celsius^鈩� Studio warpage/stress analysis simulation results have been validated. Thermal and voltage impacts on power/IR/STA are also enabled and verified inside the Cadence Integrity 3D-IC Platform for TSMC 3DFabric.

The AI factories鈥� insatiable appetite for data is increasing the requirements for interconnects and pushing power envelopes. Cadence has a for efficiently moving data between chiplets and across data centers, including Universal Chiplet Interconnect Express^鈩� (UCIe^鈩�) 1.0, PCI Express^庐 (PCIe^庐) 6.0 and the world鈥檚 first silicon-proven GDDR7 on TSMC N3, running at 32Gbps, which provides the best price/performance for AI interfaces in both data centers and network edges. To address the growing communication challenges between these chips, Cadence silicon photonics design enablement solutions support TSMC鈥檚 Compact Universal Photonic Engine (COUPE).

TSMC and Cadence are jointly collaborating with the leaders in the automotive space. As the silicon content in today鈥檚 automotive designs continues to grow, IP development for current and future process nodes, such as TSMC N5A and later N3A, is even more critical.

TSMC and Cadence have also collaborated to showcase the accuracy and scalability offered by 颁补诲别苍肠别鈥檚 front-to-backend chip design flows on the Cloud for TSMC鈥檚 advanced process nodes. Through this collaboration, mutual customers can shorten design schedules by adopting 颁补诲别苍肠别鈥檚 wide range of .

鈥淭SMC and Cadence have a long-standing, successful partnership that turns the world鈥檚 designs into silicon reality,鈥� said Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. 鈥淭ogether, we are revolutionizing the future of silicon design with AI-powered EDA software, enabled for TSMC鈥檚 latest process technologies. Our ongoing collaboration on innovative solutions for next-generation technologies like TSMC A16 and 3Dblox is paving the way for the AI factories of tomorrow.鈥�

鈥淚n collaboration with Cadence, we鈥檝e successfully enabled AI-optimized design flows for TSMC鈥檚 N2 technology and are driving advancements in 3D-IC design,鈥� said Dan Kochpatcharin, head of Ecosystem and Alliance Management Division at TSMC. 鈥淭his marks a significant leap forward in digital and custom solutions, paving the way for the technology innovations that will power the AI infrastructure.鈥�

About Cadence

Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world鈥檚 most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For 10 years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at .

漏 2024 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at are trademarks or registered trademarks of Cadence Design Systems, Inc. UCIe Consortium, Universal Chiplet Interconnect Express and UCIe are trademarks of the UCIe Consortium. PCI Express and PCIe are registered trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

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Source: Cadence Design Systems, Inc.

FAQ

What are the key technologies Cadence and TSMC are collaborating on for AI-driven designs?

Cadence and TSMC are collaborating on AI-driven digital and custom design flows for TSMC's N2P and N3 technologies, A16 design solutions for PPA optimization, and 3D-IC solutions using the Cadence Integrity 3D-IC Platform supporting 3Dblox features.

What is the significance of Cadence's silicon-proven GDDR7 IP for CDNS stock?

Cadence's silicon-proven GDDR7 IP running at 32Gbps on TSMC N3 technology demonstrates the company's leadership in high-performance memory interfaces, which is important for AI applications and could potentially drive demand for Cadence's IP solutions, positively impacting CDNS stock.

How is Cadence (CDNS) supporting TSMC's advanced process nodes in the cloud?

Cadence is collaborating with TSMC to showcase the accuracy and scalability of Cadence's front-to-backend chip design flows on the Cloud for TSMC's advanced process nodes, enabling mutual customers to shorten design schedules by adopting Cadence's wide range of Cloud solutions.

What is the role of Cadence's Celsius Studio in the collaboration with TSMC for CDNS investors?

Cadence's Celsius Studio provides mechanical analysis enablement for TSMC 3DFabric, including validated warpage/stress analysis simulation results. This capability is important for 3D-IC technologies and could strengthen Cadence's position in the advanced packaging market, potentially benefiting CDNS investors.

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